library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;

entity ram is
  port (
    clock        : in  std_logic;
    we, oe       : in  std_logic;
    address      : in  std_logic_vector(9 downto 0);
    bidir        : inout  std_logic_vector(15 downto 0)
  );
end entity ram;

architecture a of ram is

   type ram_type is array (1023 downto 0) of std_logic_vector(15 downto 0);
   signal ramMemory : ram_type;
begin

  RamProc: process(clock) is

  begin
    if rising_edge(clock) then
       if we = '1' then
          ramMemory(to_integer(unsigned(address))) <= bidir;
       elsif oe = '1' then
          bidir <= ramMemory(to_integer(unsigned(address)));
       else
          bidir <= "ZZZZZZZZZZZZZZZZ";
       end if;
    end if;
  end process RamProc;

end architecture a;